A FIFO is a First In/First Out buffer that can queue a burst of outgoing characters for transmission, or save a set of incoming characters until the host can read them. This function cannot accept incoming data; consult its glossary entry for details. Consult their glossary entries for details. The QScreen allows the details of the synchronous communications protocol to be customized for compatibility with a variety of peripherals. Setting the MSTR bit initializes the QScreen as a master, and clearing the MSTR bit initializes it as a slave. The interface can be used to support analog to digital and digital to analog converters, networks of many computers controlled by a single master, or networks of devices controlled by several coordinated masters. There are a variety of ways the MOSI, MISO, SCK and /SS pins on your QScreen Controller can be connected. In this example, the QScreen Controller selects the serial A/D by outputting a LOW signal on /SS. The next section describes the registers that configure and control the QScreen Controller’s SPI. This section also defines the logic states 1 (off) and 0 (on), by the polarity between A and B terminals.

The RS422 receiver converts the differential signal to the 0 to 5 volt logic signal required by the UART circuitry. A UART is a Universal Asynchronous Receiver/Transmitter that converts parallel data from the host processor (any Mosaic controller) into a serial data stream. If the /SS pin of the master is an input and if a low input level is detected, the processor sets the MODF bit in the SPI status register a "mode fault" condition. After a data transfer is initiated by writing to the SPDR data register, the processor may poll the SPSR status register until the SPIF flag is set. The status of a device as master or slave determines how the various pins must be configured. The CPHA bit determines whether data is valid on the leading or trailing edge of the clock. If the clock idles in the high state, the leading edge of the clock is a falling edge. With careful design, many peripherals can communicate via the SPI, and powerful multi-processor systems can be linked using this high speed bus. The SCK pin’s synchronous clock signal has configurable phase, polarity and baud rate so that it can interface to a variety of synchronous serial devices.

The CPOL, CPHA, SR1 and SPR0 configure the SCK pin’s clock polarity, clock phase, and clock rate. So long as the error between the actual baud rate and that specified is less than 1.5% (or the error between transmitter and receiver is less than 3%) there should be no communication errors. The RS232 driver and receiver use separate conductors on the serial cables, enabling full duplex communications. Each of the two UARTs on the wildcard is capable of full-duplex communications, meaning that both transmission and reception can occur simultaneously (although the RS485 protocol is half duplex as explained below). The UART Wildcard implements these optional RS232 modem handshaking signals on channel 1. The handshaking signals can be disabled and/or ignored by applications that do not need them. Port to modem communications usually use 300, 1200, 2400, 4800, 9600, 19200, 38400, 57600 and 115200 baud. The actual baud rate produced differs from that requested by a small error owing to rounding of an internal divisor. Finally, for master devices, the SPR1 and SPR0 bits determine the baud rate at which data is exchanged.

There are three flag bits implemented in the SPSR (SPI status register). The SPIF is set when a data transfer is complete, and is cleared by a read of the SPSR status register, followed by a read or write to the SPDR data register. Once the data has been exchanged, a flag bit in the SPSR status register is set to indicate that the transfer is complete. Thus, resetting the SPIF flag is very simple. This makes utilizing RS485 simple. Why use a RS232 - RS485 /RS422 converter? And what is a RS232 to RS422 converter? It is faster and much more versatile than the older RS232. The existence of an RS485 port on the socket makes it even a little bit more difficult. Even parity means that the bits sum to an even number, and odd parity means that the bits sum to an odd number. The CPOL and CPHA bits configure the synchronous clock polarity and phase and specify when valid data is present on the MISO and MOSI data lines. To interface devices that support synchronized serial interfaces, but are not configurable like the QScreen, rs485 cable determine the device’s requirements for clock phase and polarity and configure the QScreen’s CPHA and CPOL accordingly.